CMOS Design of Low Power High Speed NP Domino Logic

A low cost design and simple to implement, CMOS NP Domino logic is presented. The NP Domino logic designs require fewer transistors and are compatible with full Domino logic. The performance of NP Domino logic is also better compared to the standard Domino logic implementations. Dynamic domino logic are very good but had many challenges like monotonicity, leakage, charge sharing and noise problems. These problems are totally eliminated in the CMOS NP Domino logic (which is also known as Zipper circuits) without any penalty in performance or silicon area utilization. This paper compares NP Domino logic with static CMOS and domino (dynamic) logic design implementations.